Role : STA Lead

Job Summary :

We are looking for an experienced STA Lead to lead full-chip timing closure, sign-off convergence, and SDC constraint management for advanced-node SoCs.

The role requires deep expertise in Synopsys PrimeTime, multi-corner - multi-mode (MCMM) analysis, low-power design, and ECO closure, along with the ability to drive cross-functional sign-off activities and mentor junior engineers.

Key Responsibilities :

- Own full-chip timing closure and sign-off convergence for advanced-node SoCs.

- Manage and maintain SDC timing constraints.

- Perform timing analysis using Synopsys PrimeTime and MCMM methodologies.

- Drive low-power design timing requirements and ECO closure.

- Coordinate cross-functional sign-off activities to ensure successful tape-outs.

- Mentor junior layout and timing engineers throughout the design and sign-off process.

Required Skills :

- 13+ years of experience in STA and physical design.

- Deep expertise in Synopsys PrimeTime.

- Strong knowledge of multi-corner - multi-mode (MCMM) analysis.

- Expertise in SDC constraint management, low-power design, and ECO closure.

- Experience leading cross-functional sign-off execution and mentoring junior engineers.