Interconnect IP Post-Silicon Debug Engineer

Location : Bangalore, India

Experience : 5+ Years

Job Summary :

ACL Digital is seeking an experienced Post-Silicon Debug Engineer to support silicon enablement and debug of high-performance interconnect IP for next-generation processor and SoC platforms.

The role focuses on validating interconnect functionality on silicon, investigating system-level functional and performance anomalies, and supporting the debug of routing configurations and new interconnect features.

The ideal candidate should have a strong understanding of computer architecture, cache coherency, memory ordering, and SoC power management, along with practical programming and hardware lab debugging skills.

Key Responsibilities :

- Perform post-silicon validation and debug of interconnect IP functionality, routing configurations, and system-level use cases.

- Develop and execute debug experiments to investigate functional failures, power-related issues, and performance anomalies observed on silicon.

- Analyze debug data and system behavior to identify root causes of interconnect and SoC-level issues.

- Collaborate with architecture, design verification, firmware, software, and post-silicon teams to resolve complex silicon issues.

- Support silicon initialization and configuration by working with firmware and software teams on appropriate settings and workarounds.

- Investigate issues involving cache coherency, memory ordering, memory management, and interconnect behavior.

- Work with laboratory debugging equipment, including oscilloscopes and logic analyzers, to support silicon-level investigations.

- Contribute to Design-for-Debug (DFD) requirements to improve observability and debug capabilities in future silicon designs.

- Document debug findings, validation results, and root-cause analysis for cross-functional engineering teams.

Required Skills and Qualifications :

- 5+ years of experience in post-silicon validation, silicon debug, SoC validation, or hardware debug engineering.

- Strong understanding of computer architecture and SoC interconnect concepts.

- Knowledge of cache coherency, memory ordering, and Memory Management Unit (MMU) concepts.

- Understanding of SoC power management and system-level performance behavior.

- Programming proficiency in Python and/or C for debug automation, data analysis, and validation activities.

- Familiarity with hardware description languages such as Verilog or VHDL.

- Hands-on experience with laboratory debug tools, including oscilloscopes and logic analyzers.

- Strong problem-solving skills and the ability to investigate complex hardware and system-level failures.

Preferred Skills :

- Experience debugging high-performance processor interconnects or SoC fabrics.

- Familiarity with silicon bring-up, system-level validation, and hardware-software interaction.

- Exposure to Design-for-Debug methodologies and debug trigger development.

- Experience supporting processor, server, or AI/ML hardware platforms.

Role Expectations :

The candidate should be capable of independently investigating silicon-level failures, developing effective debug strategies, and working across architecture, firmware, software, and validation teams to improve system functionality and performance.