Role : Physical Design Engineer

ACL Digital is looking for a Physical Design Engineer to lead end-to-end RTL-to-GDSII execution for high-performance FinFET ASICs across 16nm - 5nm and dual-patterning technology nodes. The role focuses on physical implementation, timing and power optimization, physical verification, and automated design flow development.

Key Responsibilities :

- Drive end-to-end RTL-to-GDSII implementation, including floorplanning, synthesis, clock tree synthesis (CTS), and place-and-route.

- Perform timing closure, parasitic extraction, crosstalk analysis, and EM/IR analysis.

- Execute physical verification, including DRC and LVS.

- Optimize clock and power gating, scan stitching, and logic equivalence.

- Manage IP integration and collaborate with SoC architects, CAD, and design teams.

- Develop and automate design flows using Tcl, Perl, and Python.

Required Skills :

- 6+ years of experience in physical design for high-performance FinFET ASICs.

- Experience with 16nm - 5nm and dual-patterning technology nodes.

- Proficiency in Synopsys tools : Fusion Compiler, ICC2, DC, PrimeTime, and StarRC.

- Experience with Cadence Innovus and Genus, Mentor Calibre, and Apache Redhawk.

- Strong knowledge of timing closure, physical verification, clock/power gating, scan stitching, logic equivalence, and IP integration.

- Scripting experience in Tcl, Perl, and Python.