The RTL Verification Engineer is a crucial technical role requiring 48 years of experience in the semiconductor industry, focusing on the functional verification of complex digital designs.

Located in Bangalore or Thiruvananthapuram, the incumbent will primarily work on IP, module, and subsystem levels, ensuring design correctness and adherence to specifications.

The role requires expertise in UVM-based methodologies, rigorous debugging skills, and proficiency in analyzing standard bus architectures like AXI and APB.

Job Summary :

We are seeking a skilled RTL Verification Engineer (48 years) to specialize in the functional verification of complex digital designs at the IP and module levels. The ideal candidate will develop and maintain UVM-based test environments, formulate detailed verification plans, and perform rigorous functional verification using industry-standard methodologies. Key responsibilities include conducting in-depth debugging using tools like Verdi or SimVision, performing protocol-level analysis (AXI, APB), and collaborating closely with design engineers to achieve verification completeness and functional closure.

Key Responsibilities and Verification Deliverables

Verification Planning and Strategy :

- Develop and formulate comprehensive verification plans based on detailed design specifications and complex protocol-level requirements.

- Work primarily in functional verification of complex digital designs, focusing on IP, module, and subsystem levels.

UVM Environment Development :

- Design, develop, and maintain robust UVM-based test environments, testbenches, and testcases using SystemVerilog and the UVM standard.

- Perform IP-level, module-level, and system-level RTL functional verification using industry-standard methodologies, including constrained-random verification.

Debugging and Protocol Analysis :

- Conduct debugging and analysis of DUT (Design Under Test) failures, performing meticulous waveform checks and resolving environment issues.

- Collaborate with RTL design engineers to efficiently identify root causes, resolve functional bugs, and improve design quality.

- Work with tools such as Verdi, SimVision, or similar for waveform analysis and debugging.

- Perform protocol-level analysis for interfaces such as AXI, APB, or other relevant bus architectures (e.g., AHB, PCIe).

Verification Closure and Reporting :

- Execute regression suites efficiently across different platforms and configurations.

- Monitor coverage metrics (code, functional, assertion) and drive activities to ensure verification completeness and sign-off.

- Document verification results, update test plans, and actively participate in design/verification reviews.

Mandatory Skills & Qualifications :

- Experience : 4 - 8 years in RTL functional verification.

- Methodology : Strong experience with UVM-based test environments, testbenches, and testcases.

- Language : Proficiency in System Verilog and Verilog/VHDL for design interaction.

- Bus Protocols : Experience performing protocol-level analysis for interfaces such as AXI, APB, or similar industry-standard bus architectures.

- Tools : Working experience with waveform analysis and debugging tools such as Verdi, SimVision, or similar.

- Process : Proven ability to develop and formulate verification plans and execute regression suites.

Preferred Skills :

- Experience with Formal Verification techniques or Assertion-Based Verification (SVA).

- Knowledge of scripting languages (Python/Perl) for automation and flow management.

- Experience with performance verification and power-aware verification (UPF).

- Familiarity with FPGA or emulation platforms for accelerated verification.