We are looking for an experienced verification engineer.

What candidate will do :

- Develop a comprehensive verification planning, including specifications.

- Architect and enhance state-of-the-art verification environments.

- Implement and maintain UVCs, ensuring every corner of the design is verified.

- Drive both random and directed testing strategies to uncover hidden bugs.

- Leverage advanced coverage techniques to ensure top-tier verification completeness.

- Champion continuous improvement in product quality, efficiency, and workflows.

Help in setting up Team

Take Interviews and lead the team

Qualification :

- A Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- Expertise in ASIC or FPGA verification at IP, sub-system, and chip levels, using SystemVerilog UVM. Possibly 12 years of experience in Verification.

- Hands On experience designing UVM test environments and driving coverage closure

- An insatiable curiosity, ready to learn something new daily and apply it to make a real difference.

- Creative problem-solving skills-you see challenges as opportunities for innovation.

- A collaborative spirit and the ability to thrive independently, with exceptional communication skills.

- A results-oriented mindset with a passion for continuous improvement, always seeking more innovative, faster solutions.