iRage - FPGA Engineer - VHDL/Verilog

SensoVision - RTL Design Engineer - VHDL/Verilog

Happiest Minds - Senior ZeBu Emulation Engineer - Pre Silicon Validation

Principal/Lead RTL Design Engineer - ASIC/SoC

Senior RTL Design Engineer - ASIC/SoC

RTL Design Engineer

Design Verification Engineer - System Verilog

Design Engineer - RTL/System Verilog

ACL Digital - Post-Silicon Debug Engineer - SoC Platform

ACL Digital - RTL Design Engineer - System Verilog

ACL Digital - Verification/Firmware Engineer

Principal Engineer - Systems Validation