System Analyst

Western Digital - Staff VLSI Design Engineer

Cisco - Technical Leader - FPGA Design

Senior Verification Engineer - Mixed Signal

Architect/Lead - Design and Verification - SOC/IP, SystemVerilog/UVM, SOC, RISC-C, Semiconductor Domain

ASIC Design Verification Engineer - Verilog/UVM

Senior Engineer I - SoC Design

VLSI Verification Engineer

Swedium Global - Senior ASIC Verification Engineer - UVM/System Verilog

Senior Design Verfication Engineer - UVM/System Verilog

Proxelera - Senior/Principal ASIC Design Verification Engineer - SoC/Subsystem