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Gate Level Simulation Design Verification Engineer
Multiple Locations
DFX/DFT Verification Engineer
Design Verification Engineer - ASIC/SoC
PCI-e Design Verification Engineer - Ethernet/CXL/USB/UVM
Design Verification Engineer - UVM/ASIC
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Modernize Chip Solutions - RTL Integration Engineer
Bangalore
Modernize Chip Solutions - Design Verification Engineer - SerDes/SoC
Western Digital - Staff VLSI Design Engineer
Tessolve - Lead RTL Design Engineer
Bangalore/Chennai/Hyderabad
ASIC Engineer - SoC/Firmware
Senior ASIC Verification Engineer - RTL
Hyderabad/Bangalore
DFT Engineer - SoC
Architect/Lead - Design and Verification - SOC/IP, SystemVerilog/UVM, SOC, RISC-C, Semiconductor Domain
Principal Engineer - Systems Validation
VLSI Verification Engineer
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