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Full Chip Physical Verification Engineer - SoC/ASIC

5 - 12 yrs

Chennai

Static Timing AnalysisPhysical VerificationPhysical DesignChipsetEmbedded SystemSoCASIC+5+2

Posted 2 months ago

Static Timing Analysis Engineer - RTL/SoC

5 - 12 yrs

Bangalore

Static Timing AnalysisRTLSoCASICEmbedded System+3

Posted 2 months ago

Physical Design Engineer - Floor Planning

7 - 12 yrs

Bangalore

Static Timing AnalysisPhysical DesignFloor PlanningEDAPhysical Verification+3

Posted 2 months ago

Senior Physical Design Engineer

5 - 10 yrs

Bangalore/Chennai

Static Timing AnalysisPhysical DesignFloor PlanningPrimetimePhysical Verification+3

Posted 2 months ago

Hardware Design Engineer III - Static Timing Analysis

6 - 8 yrs

Bangalore

Static Timing AnalysisHardware DesignSoCPhysical DesignASIC+3

Posted 2 months ago

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Hardware Engineer III - Physical Design

5 - 7 yrs

Hyderabad

Static Timing AnalysisHardware DesignPhysical DesignEDASynopsys+3

Posted 2 months ago

Sykatiya Technologies - DFT Design Engineer - ATPG/MBIST

3 - 15 yrs

5-45 LPA

Bangalore/Hyderabad

Static Timing AnalysisDFTATPGMBISTEmbedded System+3

Posted 2 months ago

Senior Engineer/FPGA Design Engineer

5 - 8 yrs

Chennai

Static Timing AnalysisFPGA DesignRTL DesignVHDLVerilogSynthesisSERDES+5+2

Posted 2 months ago

STA & Synthesis Engineer

5 - 10 yrs

Malaysia

Static Timing AnalysisSynthesisRTLDFTPhysical Design+3

Posted 2 months ago

Physical Design Engineer - Static Timing Analysis

6 - 15 yrs

Hyderabad/Pune

Static Timing AnalysisPhysical DesignFloor PlanningSynthesisVLSITiming ClosureASIC+5+2

Posted 2 months ago

Physical Design Engineer

6 - 10 yrs

Hyderabad/Pune

Static Timing AnalysisPhysical DesignTiming ClosurePhysical VerificationDRC/LVS+3

Posted 2 months ago

Leadsoc Technologies - Full Chip Physical Design Architect

12 - 15 yrs

Bangalore

Static Timing AnalysisChipsetPhysical DesignSoCEDAPhysical Verification+4+1

Posted 3 months ago

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Leadsoc Technologies - Senior Memory Layout Engineer

5 - 8 yrs

Bangalore

Static Timing AnalysisMemory LayoutSoCFloor PlanningMemory Design+3

Posted 3 months ago

Physical Design Lead

8 - 12 yrs

Multiple Locations

Static Timing AnalysisPhysical DesignRTLPhysical VerificationFloor Planning+3

Posted 3 months ago

IP DFT Verification Engineer

3 - 7 yrs

Bangalore

Static Timing AnalysisDFTVerificationIP NetworkingMBISTATPG+4+1

Posted 3 months ago

Ambient Scientific - RTL Design Lead/Manager

10 - 13 yrs

Bangalore

Static Timing AnalysisRTLSystem VerilogSoCVerilog+3

Posted 4 months ago

Physical/Backend Engineer - VLSI/RTL

5 - 15 yrs

Bangalore

Static Timing AnalysisVLSIRTLRTL DesignSoCDFTVerificationPhysical Design+6+3

Posted 4 months ago

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