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STA & Synthesis Engineer

5 - 10 yrs

Malaysia

RTLStatic Timing AnalysisSynthesisDFTPhysical Design+3

Posted 2 months ago

Lead DFT Engineer/Manager

Bangalore

Embedded Software Engineer

8 - 12 yrs

Bangalore

RTLSystem ValidationEmbedded SystemSoCFirmwareEmbedded CEmbedded System DesignRTOSDevice Driver+7+4

Posted 2 months ago

Principal CAD Engineer

8 - 13 yrs

Hyderabad/Bangalore

RTLCADHPCEDA+2

Posted 3 months ago

Physical Design Engineer - RTL/DFT

5 - 12 yrs

Bangalore

RTLPhysical DesignRTL DesignDFT+2

Posted 3 months ago

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Senior Digital Frontend Design Engineer

5 - 10 yrs

Bangalore

RTLASICFrontend ArchitectureATPGSystem Verilog+3

Posted 3 months ago

Happiest Minds - FPGA RTL Design Engineer

10 - 12 yrs

Multiple Locations

RTLFPGARTL Design5GWireless OperationsEthernet PortVector Packet ProcessingDatapathVHDL+7+4

Posted 4 months ago

Leadsoc Technologies - Full Chip Physical Design Architect

12 - 15 yrs

Bangalore

RTLChipsetPhysical DesignSoCEDAPhysical Verification+4+1

Posted 3 months ago

Lead RTL Design Engineer

8 - 12 yrs

Bangalore

RTLRTL DesignSystem VerilogFPGAVerilogIP Design+4+1

Posted 3 months ago

SoC Architect - RTL Design

10 - 25 yrs

Bangalore/Hyderabad/Chennai

RTLSoCRTL DesignSoC VerificationIP Networking+3

Posted 3 months ago

SystemC Programmer - Embedded System

4 - 8 yrs

Noida

RTLSystemCCC++Embedded System+3

Posted 3 months ago

Senior Pre-Post Silicon Embedded Engineer

8 - 12 yrs

Bangalore

RTLEmbedded SystemCFirmwareDevice DriverSoC+4+1

Posted 3 months ago

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DFT Engineer - SoC

5 - 7 yrs

Chennai/Bangalore

RTLDFTMBISTSoCPhysical Design+3

DFT Engineer - ATPG

Bangalore

RTL Design Engineer - System Verilog

5 - 12 yrs

Multiple Locations

RTLRTL DesignSystem VerilogEmbedded SystemASICVerification+4+1

Posted 3 months ago

Senior DFT Engineer - RTL/SoC

4 - 11 yrs

Multiple Locations

RTLDFTSoCMBISTATPGSynopsysSystem Verilog+5+2

Posted 3 months ago

Design Verification Engineer - SoC

5 - 14 yrs

Multiple Locations

RTLVerificationDesign VerificationUVMASICSystem VerilogSoC+5+2

Posted 3 months ago

Mirafra Technologies - Formal Verification Engineer

5 - 10 yrs

Bangalore

RTLVerificationSoCSystem Verilog+2

Posted 3 months ago

Physical Design Lead

8 - 12 yrs

Multiple Locations

RTLPhysical DesignStatic Timing AnalysisPhysical VerificationFloor Planning+3

Posted 3 months ago

DFT Engineer - ASIC/SoC Designs

6 - 9 yrs

Multiple Locations

RTLDFTASICSoCPhysical Design+3

Posted 3 months ago

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