- Power Optimization : Experience with low-power design techniques and methodologies, including the use of the Unified Power Format (UPF).

- Timing Optimization : Proficiency in static timing analysis (STA) and experience with design constraints using the Synopsys Design Constraints (SDC) format.

- Functional Safety Analysis : Deep understanding of functional safety concepts and standards (e.g., ISO 26262), and experience with related analysis techniques like FMEDA and FTA.

- Experience with industry-standard Electronic Design Automation (EDA) tools from vendors such as Synopsys, Cadence, or Siemens EDA.

- Proficiency in hardware description languages (HDLs) such as Verilog and SystemVerilog.

- Strong scripting skills in Python and Tcl for tool automation and flow development.

- Solid understanding of the chip design and implementation flows, from RTL to GDSII.

- Excellent problem-solving, debugging, and analytical skills.

- Strong communication and presentation skills, with the ability to explain complex technical concepts to both technical and non-technical audiences.

Requirements :

Required Qualifications :

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- 5+ years of hands-on experience in chip design, with a strong focus on RTL design, synthesis, static timing analysis (STA), or power integrity.