Posted on: 19/06/2026
Description :
Position : VLSI design engineer
Experience : 8+Yrs
Work location : Bangalore, India ( all 5 days work from office)
What youll be doing :
- Drive chip-level integration for advanced GPU networking silicon projects.
- Collaborate with architecture, RTL design, verification, FV and physical design teams to ensure seamless integration and optimal performance.
- Develop and maintain integration flows, methodologies, and automation to improve efficiency and quality.
- Perform RTL synthesis, timing analysis, and support verification and post-silicon activities.
- Handle Clock Domain Crossing (CDC) checks and ensure robust design practices.
- Work closely with multiple teams across architecture, micro-architecture, backend, and firmware to deliver high-quality silicon.
- Contribute to state-of-the-art technologies delivering industry-leading throughput and ultra-low latency for GPU networking solutions.
What we need to see :
- B.Sc. in Electrical or Computer Engineering
- 8+ years of experience in chip design, integration, RTL design and/or verification
- Strong knowledge of Verilog /System Verilog and RTL design principles.
- Hands-on experience with CDC analysis, synthesis, and timing closure.
- Familiarity with EDA tools (Synopsys, Cadence, Mentor) and scripting languages (Python, TCL).
- Excellent communication skills and ability to work in a collaborative, fast-paced environment.
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Posted in
Semiconductor/VLSI/EDA
Functional Area
Embedded / Kernel Development
Job Code
1646496