VHDL/FPGA Design Engineer

Job Responsibilities :

- Design and implement high-performance digital blocks for complex communication coding using VHDL.

- Perform RTL development, simulation, writing test benches, and debugging.

- Define and manage timing constraints, utilizing advanced synthesis and timing analysis tools (e.g., Xilinx Vivado suite).

- Participate in module architecture, specification reviews, and design discussions.

- Carry out block-level design verification to ensure functionality and performance.

- Work on SoC integration, including processor cores and standard peripherals.

- Gain exposure to and apply communication protocols in FPGA/SoC design.

- Debug HDL codes efficiently by identifying, analyzing, and resolving design issues.

- Leverage strong knowledge of SoC architecture, particularly Xilinx Zynq SoC platforms.

Desired Candidate Profile :

- Strong expertise in VHDL and RTL design methodologies.

- Hands-on experience with FPGA design tools such as Xilinx Vivado.

- Good understanding of SoC integration and architecture.

- Exposure to communication protocols and digital design concepts.

- Problem-solving skills with a focus on debugging and optimization.

- Excellent communication and teamwork abilities.