- Define and implement verification strategies and test plans for DDR memory interface designs.

- Develop UVM/SystemVerilog-based testbenches and reusable verification components.

- Perform protocol-level verification for DDR memory interfaces and validate compliance.

- Collaborate with architecture, RTL, and system teams to understand design intent and corner cases.

- Own functional coverage, regression setup, and closure.

- Integrate DDR models, controllers, PHYs, and validate their interactions.

- Debug and resolve simulation failures and functional issues.

- Drive code and functional coverage improvements to ensure thorough verification.

- Lead or participate in technical reviews and mentor junior engineers.

Required Skills :

- 10+ years of hands-on experience in ASIC/IP/SoC verification.

- Strong expertise in SystemVerilog, UVM, and functional coverage methodology.

- In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols.

- Experience with DDR controllers, PHY integration, and JEDEC standards.

- Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc.

- Good scripting skills in Python, Perl, or Shell for automation and regression management.

- Excellent debugging and problem-solving skills.

- Familiarity with AXI/AHB protocols and interconnects is a plus.

- Experience working with memory models and timing analysis.

Preferred Qualifications :

- Experience with post-silicon validation or DDR hardware bring-up.

- Knowledge of formal verification tools and techniques.

- Experience with low power verification and timing closure tools.