Verification Engineer - RISC-V/SoC

Description :

Job Title :

Senior / Mid-Level Verification Engineer - RISC-V SoC

About the Role :

We are seeking a Verification Engineer to strengthen our RISC-V verification capability. In this role, you will extend existing verification environments, ensure functional correctness of cache and cluster designs, and contribute to formal and emulation-based verification.

Key Responsibilities :

- Extend and maintain the existing RISC-V verification environment.

- Verify cluster and cache subsystems against defined verification targets.

- Perform formal verification, focusing on cache coherence properties.

- Develop and support emulation platforms that boot Linux and run agreed AI applications.

- Work closely with design teams to identify, debug, and close functional issues.

- Contribute to verification planning, coverage, and sign-off activities.

Required Skills & Experience :

- Strong experience in digital verification methodologies.

- Experience with SystemVerilog and verification environments.

- Understanding of cache architectures and coherence behavior.

- Experience with formal verification techniques.

- Ability to debug complex SoC-level issues.

Preferred Skills :

- RISC-V verification experience.

- Emulation or FPGA-based verification exposure.

- Linux bring-up or system-level validation experience.

What We Offer :

- Work on advanced RISC-V platforms and real-world workloads.

- Flexible employment models (permanent or contract).

- Exposure to full verification flow from block to system level.