Description :

Job Overview :

We are looking for a Senior Verification Engineer with strong expertise in ASIC/SoC design verification to lead and execute complex verification initiatives.

The ideal candidate will play a key role in defining verification strategies, driving coverage closure, mentoring junior engineers, and ensuring high-quality delivery of silicon across IP, subsystem, and SoC levels.

Key Responsibilities :

- Define and own verification plans, strategies, and methodologies for IPs, subsystems, and SoCs

- Lead the development and maintenance of SystemVerilog/UVM-based verification environments

- Drive coverage closure, including functional and code coverage, and ensure verification completeness

- Perform subsystem-level and SoC-level verification, including integration and corner-case testing

- Verify high-speed protocols and complex IPs against specifications

- Debug complex functional issues, analyse simulation failures, and lead root cause analysis efforts

- Collaborate closely with design, firmware, architecture, and validation teams

- Review verification code, testbenches, and methodologies to ensure quality and reusability

- Mentor and guide junior verification engineers and contribute to team capability building

- Participate in regression management, sign-off reviews, and tape-out readiness activities

Required Experience :

- 5 to 10 years of hands-on experience in ASIC/SoC design verification

- Proven experience leading verification efforts for subsystems or full-chip designs

- Track record of successfully achieving coverage closure and verification sign-off

Technical Skills :

- Strong proficiency in SystemVerilog and UVM

- Good working knowledge of C/C++ for verification models and utilities

- Solid understanding of functional, formal, GLS, power, and CPU verification methodologies

- Experience verifying high-speed protocols and complex IPs

- Strong debugging skills and familiarity with industry-standard simulators and verification tools

- Experience with coverage-driven verification and regression management