We are seeking an experienced Senior Lead / Manager RTL Design Engineering to drive micro-architecture definition, RTL design, and subsystem integration for complex SoC programs.

This role demands strong hands-on technical depth combined with technical leadership and ownership of high-quality deliverables.

The individual will work closely with architecture, verification, and physical design teams to ensure robust, timing-closed, and production-ready RTL.

Key Responsibilities :

- Lead micro-architecture and RTL design for blocks and subsystems within complex SoCs

- Perform and oversee RTL coding, integration, and validation of sub-blocks into larger components

- Analyse block and subsystem requirements, identify design challenges, and propose efficient RTL solutions

- Drive design and integration of SoC interconnects, including Network-on-Chip (NoC), AXI, AHB, and APB protocols

- Define and review clocking and reset architectures, including synchronization, clock generation, and division

- Develop, review, and maintain synthesis constraints, and drive timing analysis and timing closure

- Perform and guide RTL linting, CDC, and RDC analysis, ensuring clean sign-off using tools such as Synopsys VC SpyGlass

- Collaborate with verification, physical design, and system architecture teams to ensure seamless subsystem integration

- Review RTL designs and micro-architecture documents to ensure correctness, performance, and reusability

- Provide technical leadership and mentorship to senior and junior RTL engineers

- Establish and enforce RTL quality standards, best practices, and documentation guidelines

- Ensure high attention to detail and commitment to delivering high-quality, production-ready RTL

Required Skills & Experience :

- 12 to 18 years of hands-on experience in RTL design and SoC development

- Strong expertise in micro-architecture definition, RTL coding, and subsystem integration

- Proven experience working with SoC interconnects and protocols such as NoC, AXI, AHB, and APB

- Deep understanding of clocking and reset concepts, including synchronization and clock domain management

- Strong experience in synthesis constraints development, timing analysis, and timing closure

- Extensive hands-on experience with RTL linting, CDC/RDC analysis, and debug using SpyGlass or similar tools

- Ability to analyse complex design issues and propose scalable, high-quality RTL solutions

- Experience collaborating across multi-disciplinary teams in a SoC development environment

- Strong communication, technical leadership, and problem-solving skills