The Senior Lead / Manager - RTL Design Engineer will be responsible for driving SoC architecture, micro-architecture definition, RTL development, and integration of complex digital subsystems. This role requires deep technical expertise in RTL design, timing, and quality checks, along with the ability to lead design activities and collaborate across cross-functional teams to deliver high-quality silicon.

Key Responsibilities :

- Lead architecture and micro-architecture development for complex RTL blocks and SoC subsystems

- Perform RTL coding and integration of sub-blocks into larger SoC components

- Analyze block and subsystem requirements, identify design challenges, and propose optimal technical solutions

- Own and review designs involving key SoC components and interconnects, including Network-on-Chip (NoC) AXI, AHB, and APB protocols

- Drive robust clocking and reset architecture, including synchronization, clock generation, and clock division

- Develop and review synthesis constraints, analyze critical timing paths, and support timing closure

- Perform RTL linting, debug errors and warnings using tools such as Synopsys VC SpyGlass

- Analyze and resolve CDC/RDC issues, ensuring clean handoff across clock and reset domains

- Collaborate closely with verification, physical design, DFT, and system teams to ensure seamless subsystem integration

- Ensure adherence to design quality, coding guidelines, and best practices

- Provide technical mentorship and guidance to junior engineers (for Lead / Manager level)

- Drive high standards of quality, completeness, and on-time delivery

Required Technical Skills :

- Strong expertise in RTL design and micro-architecture for complex SoCs

- Hands-on experience with Verilog / SystemVerilog

- In-depth knowledge of AMBA protocols (AXI, AHB, APB) and NoC architectures

- Strong understanding of clocking, reset, CDC, and RDC methodologies

- Proven experience with synthesis constraints (SDC) and timing analysis

- Hands-on expertise with RTL linting and CDC tools (e.g., VC SpyGlass)

- Experience in RTL integration and subsystem-level design ownership

- Solid understanding of the end-to-end SoC design flow

Soft Skills & Leadership Attributes :

- Strong analytical and problem-solving abilities

- High attention to detail with a commitment to first-time-right design quality

- Ability to clearly communicate technical concepts across teams

- Collaborative mindset with experience working in cross-functional environments

- Ownership-driven and accountable for deliverables

- Capability to balance hands-on technical work with design leadership