Tessolve - Senior DFT Engineer - RTL/GLS

Description :

Position : Sr. Design Engineer

Key Responsibilities :

- Develop and implement DFT architecture for IP, block-level, and SoC-level designs.

- Perform scan insertion, clock control logic integration, test point insertion, and compression architecture implementation.

- Ensure robust DFT planning aligned with design constraints, performance needs, and production test requirements.

- Generate stuck-at, transition, path-delay, and compression ATPG patterns using industry-standard tools.

- Perform DFT simulations at RTL and gate level to validate scan chains, test points, and MBIST logic.

- Conduct Gate-Level Simulations (GLS) to ensure functional correctness and coverage closure.

- Debug ATPG and simulation issues, identify root causes, and provide design fixes or tool flow improvements.

- Insert MBIST controllers, configure test algorithms, and verify memory test coverage.

- Validate BIST logic through simulation and support its integration at SoC level.

- Work extensively with tools such as Tetramax, Modus, Tessent, Design Compiler (DC) for synthesis and DFT insertion.

- Develop scripting solutions using Perl, Python, Shell, or TCL to automate repetitive processes and enhance flow efficiency.

- Optimize flows to reduce pattern generation time, simulation runtime, and improve coverage.

- Support SoC-level integration of DFT logic including scan stitching, test mode integration, and hierarchical DFT flows.

- Create comprehensive technical documentation such as uArchitecture Specifications, Integration Guides, and DFT Reports.

- Collaborate with design, verification, and physical design teams to ensure smooth DFT implementation across all stages.

- Work on debugging complex failures during RTL/GLS simulation, ATPG pattern application, and silicon bring-up.

- Analyze test coverage, identify coverage gaps, and propose enhancements to improve testability and quality.

- Provide support during silicon validation and test program development, if required.

To Be Successful in This Role, You Will :

- Demonstrate strong analytical thinking, problem-solving ability, and a proactive approach to project ownership.

- Be highly motivated, energetic, and capable of working independently as well as in cross-functional teams.

- Show strong attention to detail, technical rigor, and the ability to deliver high-quality results under tight schedules.

- Have excellent communication skills to collaborate with global teams and present technical findings clearly.

Technical Skillset Required :

- Solid understanding of DFT methodologies, scan-based testing, ATPG concepts, and compression techniques.

- Hands-on experience with Scan, ATPG, Simulation, GLS, and DFT flow setup.

- Strong command of leading EDA tools such as:

Synopsys :

- Tetramax

- DFT Compiler

- Design Compiler

Cadence:

- Modus

Mentor (Siemens) :

- Tessent tools

- Experience with MBIST insertion, configuration, and simulation.

- Strong debugging skills in simulation and gate-level environments.

- Proficiency in scripting languages like Perl, Python, Shell, TCL for automation.

- Ability to review and interpret complex SoC specifications, schematics, and uArch documentation.