- To Be Successful in This Role, You Will

- Be a self-driven, energetic individual contributor with strong ownership of end-to-end DFT deliverables.

- Enjoy working in a fast-paced environment and collaborating with cross-functional design, verification, and physical design teams.

- Demonstrate strong analytical thinking, attention to detail, and technical rigor.

- Take on the challenge of delivering robust, production-ready DFT solutions for complex, high-performance designs.

Technical Skillset Required :

- Strong knowledge of Design-for-Test (DFT) concepts and methodologies.

- Hands-on experience with DFT architecture, including scan insertion, test point insertion, compression logic, ATPG, simulation, and gate-level signoff (GLS).

- Practical experience with DFT tools from:

- Synopsys: Tetramax, DFT Compiler, Design Compiler

- Cadence: Modus

- Mentor/Siemens: Tessent tools

- Ability to optimize tool flows, debug tool issues, and support synthesis/DFT integration.

- Hands-on experience in MBIST insertion, configuration, and simulation.

- Understanding of memory test algorithms and hierarchical integration flows.

- Strong debugging capabilities in simulation, GLS, scan patterns, and ATPG coverage gaps.

- Ability to write and maintain:

- uArchitecture Specifications

- SoC Integration Specifications

- DFT guidelines and release documentation

- Good exposure to scripting for automation using:

- Perl

- Python

- Shell

- TCL

- Ability to enhance DFT flows, automate reports, and streamline validation processes.