We are seeking an experienced RV PDK Engineer to develop, maintain, and support PDK collateral for advanced semiconductor process nodes. The role involves close collaboration with foundries, EDA teams, and internal design groups to ensure accurate and robust enablement of RTL-to-GDS flows.

Key Responsibilities :

- Develop, validate, and maintain PDK collateral across multiple technology nodes

- Build and support DRC, LVS, ERC, and PERC rule decks

- Enable and validate layout, extraction, and verification flows

- Work closely with foundries to integrate and debug PDK updates

- Support EDA tool qualification (Synopsys / Cadence / Siemens)

- Validate PDKs using real customer testcases and reference designs

- Debug rule deck issues, extraction mismatches, and LVS/DRC failures

- Maintain version control, documentation, and release notes for PDK deliverables

- Collaborate with design, CAD, and methodology teams to support tape-outs

- Provide technical support to internal design teams during block and full-chip signoff

Technical Skills :

PDK & Physical Verification :

- DRC, LVS, ERC, PERC rule development and debugging

EDA Tools :

- Synopsys (IC Validator, StarRC, ICC2)

- Cadence (Virtuoso, Pegasus, Quantus)

- Siemens / Mentor (Calibre)

Layout & Signoff :

- Strong understanding of layout verification, extraction, and signoff flows

Scripting :

- Proficiency in TCL, Perl, Python, or Shell scripting

Process Knowledge :

- CMOS process technology fundamentals (FEOL, BEOL, device physics basics)

- Experience with advanced nodes (28nm and below preferred)

Soft Skills & Other Requirements :

- Strong analytical and debugging skills

- Ability to work independently and collaboratively in cross-functional teams

- Good written and verbal communication skills

- Experience working with global teams and foundry partners

- Detail-oriented with strong documentation practices