- Develop high-quality RTL using Verilog/SystemVerilog based on architecture and design specifications.

- Define and review microarchitecture for complex IPs and SoC subsystems.

- Lead RTL development and ensure quality through coding guidelines and design reviews.

- Integrate IPs into SoC and resolve integration-related issues.

- Collaborate with Architecture, Verification, Physical Design, DFT, and Firmware teams.

- Perform RTL debugging, lint, CDC/RDC, synthesis, and timing issue analysis.

- Drive design optimization for area, power, and performance (PPA).

- Mentor junior engineers and provide technical leadership.

- Participate in customer discussions, effort estimation, and project planning.

Required Skills :

- 8 - 15 years of experience in ASIC/SoC RTL Design.

- Strong RTL coding experience using Verilog/SystemVerilog.

- Expertise in Microarchitecture Design.

- Hands-on experience in SoC Integration.

- Good understanding of AMBA protocols (AXI, AHB, APB).

- Experience with Lint, CDC/RDC, Synthesis, and STA concepts.

- Strong debugging and problem-solving skills.

- Familiarity with Git/Perforce and scripting (Python/Perl/Shell) is an added advantage.

- Excellent communication and stakeholder management skills.