We are looking for an experienced Lead Design Verification Engineer to drive IP and SoC-level verification using industry-standard methodologies and tools. The role requires strong hands-on expertise in SystemVerilog/UVM, protocol verification, coverage closure, and testbench architecture, along with the ability to work in a global, multi-cultural environment.

Key Responsibilities :

- Lead IP-level and/or SoC-level verification using SystemVerilog and UVM methodologies

- Develop, integrate, and maintain UVM-based verification environments

- Integrate and customize Verification IPs (VIPs) for standard protocols

- Verify interconnect protocols such as AHB, AXI, and APB

- Verify SoC interfaces including GPIO, SPI, I2C, UART (minimum 3 interfaces)

Work on high-speed serial interfaces, such as :

- PCIe Gen 3/4, USB, MIPI, DDR, or UPF

Drive coverage closure across :

- Code coverage

- Functional coverage

- Toggle coverage

- Debug complex functional and timing-related verification issues

- Prepare and review technical documentation, including :

Testbench Architecture Specifications

Verification Test Plans

- Collaborate closely with design, architecture, and validation teams across geographies

- Mentor junior verification engineers and contribute to best practices

Technical Skills :

Verification Languages & Methodologies :

- SystemVerilog, UVM

Protocols & Interfaces :

- AHB, AXI, APB

- GPIO, SPI, I2C, UART

- PCIe, USB, MIPI, DDR, UPF (any one or more)

Verification Tools :

- Synopsys VCS or Cadence Incisive/Xcelium

Scripting :

- Proficiency in Perl, Python, Shell, or TCL

Coverage & Debug :

- Strong experience in coverage analysis, closure, and debug

Soft Skills & Other Requirements :

- Experience working in a multi-national / global engineering environment

- Excellent oral and written communication skills

- Strong analytical and problem-solving abilities

- High learning agility with adaptability to new technologies and methodologies

- Proactive mindset with a strong sense of ownership and growth orientation