Job Overview :

We are seeking a Junior Verification Engineer with hands-on experience in ASIC/SoC verification to support the development and validation of complex digital designs.

The role involves building and executing verification environments, debugging functional issues, and collaborating closely with design and architecture teams to ensure high-quality silicon delivery.

Key Responsibilities :

- Develop, execute, and maintain verification environments for ASIC/SoC designs using SystemVerilog and UVM

- Create and enhance test plans, test cases, and coverage models to ensure comprehensive functional validation

- Perform functional, formal, gate-level (GLS), power, and CPU verification activities

- Verify high-speed protocols and third-party IP blocks as per specifications

- Analyse simulation failures, debug design and testbench issues, and assist in root cause analysis

- Collaborate with design, firmware, and architecture teams to resolve functional and integration issues

- Track and improve functional and code coverage metrics

- Participate in regression testing and verification sign-off activities

- Document verification strategies, test scenarios, and results

Required Experience :

- 3 to 5 years of hands-on experience in ASIC/SoC design verification

- Experience working on block-level and/or subsystem-level verification

Technical Skills :

- Strong proficiency in SystemVerilog and UVM-based verification

- Good working knowledge of C/C++ for verification utilities or reference models

- Understanding of functional, formal, GLS, power, and CPU verification methodologies

- Exposure to high-speed protocol and IP verification

- Experience with coverage-driven verification (functional and code coverage)

- Familiarity with industry-standard simulators and verification tools