We are looking for an experienced DFT Engineer to work on complex SoC designs, focusing on test architecture definition, implementation, and validation. The role involves hands-on ownership of scan, ATPG, and MBIST flows, with close collaboration across design, verification, and physical design teams.

Key Responsibilities :

- Define and implement Design for Testability (DFT) architectures for complex SoCs

- Perform scan insertion, ATPG generation, and coverage analysis

- Execute and debug RTL, gate-level, and GLS simulations related to DFT

- Implement and validate MBIST and memory test structures

- Support JTAG and boundary scan implementation where applicable

- Debug DFT-related issues across RTL, netlist, and simulation stages

- Collaborate with design, verification, and physical design teams to resolve testability issues

- Prepare and maintain technical documentation such as DFT architecture specifications and SoC integration documents

- Support manufacturing test readiness and post-silicon debug activities

Required Technical Skills :

- Strong knowledge of DFT fundamentals and architectures

- Hands-on experience with Scan, ATPG, Simulation, and GLS

- Experience with MBIST insertion and validation

- Working knowledge of JTAG and boundary scan (added advantage)

Experience using EDA tools from Synopsys, Cadence, or Siemens EDA (Mentor), including :

- Tetramax

- Modus

- Tessent

- Design Compiler (DC)

- Strong simulation debugging skills

- Experience in writing and reviewing technical documentation

Proficiency in scripting using one or more of the following :

- Perl

- Python

- Shell

- TCL

Qualifications & Experience :

- Bachelors or Masters degree in Electronics, Electrical Engineering, or a related field

- 5 - 7 years of relevant experience in DFT for SoC or ASIC designs

- Strong analytical and problem-solving skills

- Ability to work effectively in cross-functional engineering teams

- Good written and verbal communication skills