About the Role :

Were looking for a hands-on RISC-V System IP DV Engineer to design, implement, and evolve state-of-the-art verification infrastructure for next-generation System IPs including interrupt controllers, IOMMU, power management, and debug/DFD modules that will integrate into high-performance RISC-V CPU clusters.

This role is ideal for engineers who thrive on building from scratch, innovating verification methodologies, and working closely with world-class CPU designers and architects. You will own verification end-to-end, from testbench architecture to coverage closure, ensuring silicon-proven reliability.

Key Responsibilities :

- Architect, develop, and maintain UVM/SystemVerilog-based verification environments for complex RISC-V System IPs.

- Define, execute, and track comprehensive verification plans across IP, subsystem, and SoC integration levels.

- Design reusable verification components, checkers, monitors, and coverage models that scale across multiple projects.

- Drive stimulus planning, constrained-random test generation, and advanced debug strategies to validate corner cases.

- Collaborate with RTL designers, micro-architects, and software/firmware teams to validate system-level use cases (memory translation, interrupt routing, security, power/performance trade-offs).

- Ensure functional correctness and robustness across features that span multiple IPs (e.g., IOMMU + MMU + cache hierarchy interactions).

- Contribute to methodology innovation, continuous improvement of flows, and adoption of emerging verification best practices.

Who You Are :

- Strong knowledge of computer architecture fundamentals - memory hierarchy, virtual/physical memory translation, page tables, caching, and coherency.

- Proven expertise in SystemVerilog, UVM, and testbench development; exposure to C++/SystemC is a plus.

- Deep understanding of coverage-driven verification methodologies (functional/code coverage, closure strategies).

- Experience verifying complex SoC interconnects and protocols such as AXI/CHI/ACE.

- Strong debug skills with waveform analysis, assertions, and failure triaging across multi-IP scenarios.

- Self-driven and comfortable owning verification projects end-to-end with minimal supervision.

Requirements :

- Bachelors/Masters degree in Computer Engineering/Computer Science.

- 7-15 years of experience in System IP or SoC-level verification.

- Demonstrated ability to lead IP-level and subsystem-level DV projects.

- Familiarity with MMU, SMMU/IOMMU, power management flows, or interrupt controllers is strongly preferred.

- Bonus : Exposure to Python/Perl/TCL scripting for automation and regression infrastructure.

What You Will Learn & Drive :

- End-to-end ownership of verification for high-impact System IPs in RISC-V SoCs.

- Building scalable, configurable, and reusable verification frameworks for long-term SoC integration.

- Hands-on experience with IOMMU integration in modern SoCs, collaborating with RTL, performance architects, and software teams.

- Opportunity to innovate verification methodologies in a fast-paced, high-growth RISC-V ecosystem.