Position : Senior/Staff STA Engineer

Experience : 5+ Years

Location : Bangalore (On-site)

Job Summary :

Tenstorrent is seeking a skilled and detail-oriented Senior/Staff Static Timing Analysis (STA) Engineer with 5+ years of hands-on experience to ensure first-pass silicon success for our cutting-edge AI and RISC-V SoCs. The ideal candidate will have a strong foundation in STA and deep expertise in timing constraints.

This role involves leading timing closure efforts from the block level to the full-chip level, collaborating with cross-functional teams, and tackling the complexities of advanced technology nodes like 5nm and 3nm.

Key Responsibilities :

- Own STA Methodology : Define and take ownership of the STA methodology, including the development and validation of timing constraints (SDC/Tcl) across multiple corners and modes, such as functional, scan, and low-power.

- Timing Closure : Lead end-to-end timing closure efforts at both the block and full-chip levels. This includes analyzing complex timing reports, debugging and fixing setup and hold violations, and ensuring timing signoff at worst-case and best-case corners.

- Constraint Management : Meticulously review and maintain SDC constraints, validating them against design intent and ensuring completeness and correctness for all modes and corners.

- Advanced Analysis : Apply deep knowledge of MMMC (Multi-Mode Multi-Corner) flows, Clock Domain Crossing (CDC) analysis, and the proper use of timing exceptions like false and multicycle paths.

- Flow Automation : Develop and maintain robust scripts using Tcl, Perl, or Python to automate the timing flows, generate custom reports, and improve overall signoff efficiency.

- ECO Implementation : Handle Engineering Change Orders (ECOs) for both timing and functional fixes, with a strong focus on minimizing risk and turnaround time.

- Cross-Functional Collaboration : Work closely with Physical Design, RTL, DFT, and Synthesis teams to efficiently debug and resolve complex timing issues.

Required Skills & Qualifications :

- 5+ years of hands-on experience in STA for complex SoCs, spanning from block-level to full-chip analysis and closure.

- Proven expertise in developing and validating timing constraints (SDF/SDC) for various design modes and PVT (Process, Voltage, Temperature) corners.

- Strong proficiency in using industry-standard STA tools like PrimeTime, Tempus, or PTPX.

- Solid scripting skills in Tcl, Perl, or Python for flow automation and custom reporting.

- Deep experience in analyzing timing reports and performing timing closure on complex designs.

- Familiarity with CDC analysis, MMMC flows, and timing exception debugging.