Role Overview :

As a SystemC Engineer, you will be at the forefront of next-gen embedded system development, working with a team that thrives on innovation, technical excellence, and problem-solving.

You will be responsible for driving the development of Virtual Platforms for modern embedded systems, enabling software teams to develop, test, and validate software long before hardware is available.

What You Will Do :

- Architect & develop C++ and SystemC based TLM2.0 models for CPUs, peripherals, and SoC components.

- Optimize simulation performance, ensuring fast and accurate virtual testing.

- Collaborate with hardware, firmware, and software teams to define system specifications.

- Integrate SystemC models with simulators like QEMU, Synopsys Virtualizer, and other industry-standard platforms.

- Participate and contribute in Industry workgroups to define the technical standards relevant for Virtual Platforms.

- Mentor & upskill junior engineers, shaping the next generation of virtual prototyping experts.

Must-Have Technical Skills :

- Expertise in SystemC and Transaction-Level Modeling (TLM 2.0).

- Strong programming skills in C/C++, with deep knowledge of OOPS concepts.

- Hands-on experience in embedded software/firmware development.

- Strong understanding of a broad subset in SoC architecture, CPU pipelines, GPUs, Hardware Accelerators, memory subsystems, and bus protocols (e.g., AXI, PCIe, USB).

- Experience in peripheral modeling (Timers, DMA Controllers, I/O controllers, etc).

Good-to-Have Skills :

- Prior experience in developing Virtual Platforms (VPs) for semiconductor companies.

- Familiarity with simulators like QEMU, Synopsys Virtualizer, or equivalent.

- Exposure to hardware/software co-simulation methodologies.

- Understanding of Verilog/SystemVerilog for analyzing hardware designs.