Description : We are seeking a highly skilled STA Engineer with strong experience in Static Timing Analysis, convergence, and signoff for complex multi-mode, multi-voltage domain designs. The ideal candidate should possess in-depth knowledge of STA tools such as Tempus or Primetime, and have a solid understanding of timing closure, cross-talk noise, and signal integrity issues.

Key Responsibilities :

- Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-corner, and multi-voltage domain designs.

- Conduct timing analysis, validation, and debug across multiple PVT (Process, Voltage, Temperature) conditions using Tempus.

- Run Primetime and/or Tempus for STA flow optimization and ensure accurate Spice-to-STA correlation.

- Identify and resolve timing violations, setup/hold issues, and perform timing closure activities.

- Collaborate with physical design, synthesis, and design teams to ensure accurate timing signoff.

- Analyze and address cross-talk noise, signal integrity, and layout parasitic extraction issues.

- Ensure complete timing coverage and signoff quality for tape-out readiness.

Required Skills :

- Strong hands-on experience with STA tools such as Tempus (Cadence) and/or Primetime (Synopsys).

- Solid understanding of multi-mode, multi-voltage domain timing closure.

- Expertise in timing constraints (SDC) and analysis methodologies.

- Knowledge of cross-talk noise, SI (Signal Integrity), and feedthrough handling.

- Familiarity with parasitic extraction (RC) and ECO implementation.

- Strong analytical, debugging, and problem-solving skills.

- Good communication and teamwork skills.