Static Timing Analysis Engineer - PnR

Description :

Role/Skill : PTPX, Synth, CLP or PTPX, PNR, STA, CTS, UPF, DRC, LVS (DFT and Synthesis competencies), Synth, STA, EMIR, PD

Experience : 3 to 8 Years

Location : Bangalore

Job Type : C2H

Key Responsibilities :

- Run and debug static and dynamic IR analysis, EM violations, power grid checks, and ESD validation.

- Collaborate with Physical Design (PNR) teams to resolve power integrity violations and achieve sign-off.

- Ensure tape-out readiness by validating that power integrity, reliability, and foundry EM/ESD requirements are met.

- Work with CAD and methodology teams to improve power integrity flows, automation, and analysis methodologies.

- Should have worked in latest technology nodes and must have hands-on experience with RedHawk-SC (RHSC), Voltus, Fusion Compiler, and Innovus tools.

- Thank you in advance for your attention and continued support.

- Develop and optimize floorplans considering macro placement, power grid strategy, IO planning, congestion reduction, and routing feasibility.

- Execute place and route (PnR) flows including placement, CTS, routing, optimization, DRC-driven refinements, and ECO cycles.

- Perform full chip and block level Static Timing Analysis (STA) including timing closure, derates, OCV, SI aware analysis, and generation of ECOs.

- Run and debug Physical Verification (PV) flows such as DRC, LVS, Antenna, ERC, EM/IR, CLP, and signoff checks.

- Collaborate with RTL, synthesis, architecture, and verification teams to ensure seamless integration and PPA convergence.

- 5 - 7 years of hardware experience involving design and integration of large complex Sub-systems/ SoCs.

- Design experience in Multimedia Domain with good knowledge preferably on Video Codecs / Computer Vision / AI / ML/ Hardware Architecture is a plus.

- Should have knowledge of AMBA protocols - AXI, AHB, APB, with clocking/reset/debug architectures.

- Hands on experience in Low power design is required

- Hands on experience in Multi Clock designs, Asynchronous interfaces is required

- Experience in ASIC development flow such as Lint, CDC, Synthesis and CLP is required.

- Understanding of constraint development and timing closure is a plus.

- Understanding of Synthesis / Functional ECOs / timing concepts is a plus.

- Work closely with the verification and validation teams for pre/post Silicon debug

- Excellent oral and written communications skills

- Proactive, creative, curious, motivated to learn and good collaborative skills

- Knowledge of PTPX, power Artist, STA, Verdi, VCS, STA

- Knowledge of DDR LP5, CHI

- Basic power fundamentals , knowledge of power domain, UPF

- Should be able to generate vector and run VCS simulation

- Proficient in PT commands

- Experience in handling complex data path oriented Multi-million gate synthesis. Working Knowledge on Physical synthesis using tools like Genus, Fusion Compiler

- Experience in developing constraints for multi-clock domains hierarchical/flat timing analysis

- Good working knowledge in multi-power domain synthesis and structural power checks using CLP.

- Hands-on experience in Formal verification along with strong debugging skills for resolving issues/aborts.

- Good working knowledge in Pre-lyt STA and analyzing timing reports and generating timing ECOs

- Good knowledge on analyzing trade-offs and recipes for timing/area/power/congestion.

- Exposure in TCL scripting for usage in Synthesis/STA

- Knowledge on Hierarchical STA with Hyperscale is a plus

- Good team player. Need to interact with the stakeholders proactively

- Ability to debug and solve issues independently

Required Skills & Experience :

- Strong hands on experience in floorplan, PnR, STA, and PV for ASIC/SoC designs.

- Solid understanding of digital design concepts, clocking structures, power intent (UPF), and physical implementation constraints.

- Experience closing timing across multiple corners and modes.

- Familiarity with advanced node challenges (7nm/5nm/3nm or similar).

- Expertise with industry standard EDA tools such as :

1. Synopsys : PrimeTime

2. Cadence : Innovus, Tempus, Voltus, Pegasus/Calibre for PV

- Strong debugging, analytical skills, and ability to handle complex blocks independently.

- Proficiency in scripting (Tcl, Python, Shell) for flow automation and productivity.

Minimum Qualifications :

- 3-5 years Hardware Engineering experience or related work experience.