Description :

Position : STA Engineer (Static Timing Analysis)

Experience : 4 - 8+ Years

Location : Noida

Job Mode : Remote

Key Responsibilities :

Timing Constraints Development & Analysis :

- Develop, validate, and maintain block-level timing constraints (SDC) for both functional and DFT modes.

- Ensure complete and accurate enablement of modes, clocks, generated clocks, false paths, multicycle paths, case analysis, and exceptions.

- Perform thorough timing constraint reviews, ensuring alignment with design intent and clocking structures.

STA Execution & Timing Sign-Off :

- Perform setup/hold analysis, unconstrained path checks, and ensure timing QoR is met across all corners and modes.

- Run PrimeTime-based STA and validate reports for both block-level and hierarchical integration stages.

- Interact with physical design and DFT teams to enable smooth timing sign-off through various milestones.

Check Timing & QoR Validation :

- Review and resolve issues flagged during check_timing, missing constraints, unconstrained clocks, or QoR checks.

- Perform detailed constraint validation to ensure timing exceptions are accurate, justified, and validated through simulation or RTL feedback.

Clocking & Data Path Understanding :

- Strong understanding of clock tree synthesis (CTS) flow, clock definitions, clock gating structures, and skew/buffer strategies.

- Review clock tree specifications and timing characteristics such as insertion delay, latency, jitter, and clock uncertainty.

- Analyze data flow paths, combinational logic depth, and timing bottlenecks.

Timing ECO Implementation :

- Perform timing ECO analysis using PT-ECO or equivalent flows to fix setup/hold and other timing violations.

- Work closely with the physical design team to guide ECO placement, buffer/upsize suggestions, and net optimizations.

- Validate post-ECO timing and ensure clean sign-off without regression.

Cross-Functional Collaboration :

- Collaborate with RTL/Front-End design teams for deeper timing intent understanding.

- Coordinate with DFT teams to ensure constraints and timing in scan/MBIST/ATPG/LBIST modes are correctly enabled.

- Partner closely with physical design (PD) and implementation teams to drive timing closure at block and top level.

Documentation & Reporting :

- Prepare timing summary reports, ECO recommendations, and sign-off documentation.

- Maintain version-controlled timing SDC files, STA scripts, and constraints documentation.

- Provide updates to project managers and technical leads regarding timing issues, risks, and progress.

Required Technical Skills :

Tool Expertise :

Strong hands-on knowledge of :

- Synopsys PrimeTime

- PT-ECO

- STA scripting using TCL

Technical Expertise :

- Block-level timing constraints creation and validation.

- Functional & DFT timing enablement.

- Deep understanding of clocking, generated clocks, CDC considerations, and timing exceptions.

- Knowledge of timing closure methodologies at block and chip levels.

- Strong understanding of setup/hold, recovery/removal, OCV, AOCV, and derates.

- Experience with physical design flows (synthesis, PNR, CTS).

Preferred Qualifications :

- Experience with full ASIC development cycle.

- Exposure to sign-off timing environments for advanced nodes (7nm/5nm/16nm).

- Good understanding of RTL architecture, logic design, and DFT structures.

- Familiarity with scripting (TCL/Perl/Python) for automation.

Soft Skills :

- Strong analytical and problem-solving skills.

- Effective communication with multiple engineering teams.

- Ability to work independently and handle ownership of timing closure deliverables.

- Attention to detail and ability to handle complex design structure