- Define, develop, and execute SoC/Sub-system-level verification plans.

- Design and maintain SystemVerilog/UVM-based testbenches and reusable verification components.

- Verify complex IPs and interfaces including CPU, PCIe, and CXL.

- Drive coverage closure, regression management, and ensure test completeness.

- Collaborate closely with design, architecture, and validation teams to ensure design intent and quality.

- Perform Gate-Level Simulations (GLS) and assist in debugging functional and performance issues.

- Contribute to verification methodology and process improvements across projects.

Required Skills & Experience :

- 10+ years of experience in Design Verification.

- Strong proficiency in SystemVerilog and UVM methodology.

- Solid understanding of AMBA protocols (AXI, AHB, APB).

- Proven hands-on experience with CPU architectures, PCIe, or CXL.

- Exposure to SoC/Sub-system-level simulation and integration.

- Excellent debugging, analytical, and problem-solving skills.

- Experience with Gate-Level Simulations (GLS) is highly desirable.

- Strong communication skills and ability to work in a collaborative, dynamic environment