STA Engineer - VLSI Design

Description : STA Engineer (Static Timing Analysis) VLSI

Location : Bangalore, India

Experience : 4 to 10 Years

Employment Type : Full-time / Permanent

About the Role :

We are seeking an experienced STA Engineer with a strong background in VLSI design and timing closure.

The ideal candidate will be responsible for performing static timing analysis, ensuring timing convergence, and collaborating closely with design and physical implementation teams to achieve sign-off quality results for complex SoCs and ASICs.

Key Responsibilities :

- Perform Static Timing Analysis (STA) at various design stages (pre-layout, post-layout, sign-off).

- Analyze and resolve timing violations across multiple modes and corners.

- Collaborate with Physical Design, RTL Design, and Synthesis teams to drive timing closure.

- Develop and maintain timing constraints using SDC (Synopsys Design Constraints).

- Work on Clock Tree Synthesis (CTS) and timing optimization for setup, hold, recovery, and removal checks.

- Perform timing correlation between different tools (synthesis vs place & route vs sign-off).

- Manage timing reports, ECOs, and sign-off activities using industry-standard EDA tools.

- Ensure design meets all timing, signal integrity, and power performance targets.

Required Skills & Qualifications :

- Strong expertise in STA using industry-standard tools like Synopsys PrimeTime, Tempus, or GoldTime.

- Solid understanding of ASIC design flow, physical design, and timing ECO processes.

- Proficiency in timing constraints (SDC) and timing exception handling.

- Experience with multi-mode, multi-corner (MMMC) analysis.

- Good understanding of clock tree design, on-chip variation (OCV), and parasitic extraction (SPEF, RSPF).

- Familiarity with scripting languages such as Tcl, Perl, or Python for automation.

- Knowledge of low power design techniques and timing closure for advanced technology nodes (7nm/5nm preferred).

- Strong analytical and debugging skills with attention to detail.

Good to Have :

- Exposure to Physical Design (P&R) tools such as ICC2, Innovus, or Fusion Compiler.

- Experience with Formal Verification, Logic Equivalence Check (LEC), or Power analysis.

- Familiarity with DFT and Clock Domain Crossing (CDC) concepts.