We are seeking a talented Implementation Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products.

This is what you are responsible for :

- Synthesis and STA (static timing analysis).

- Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL.

- Professional experience with ECO implementation, both functional and timing closure.

- Experience with multi-clock, multi-power domain designs and multi-mode timing constraints.

- Familiarity with DFT insertion.

- Familiarity with simulation, debugging tools, and working closely with Design teams.

- Ability to collaborate with different functional teams like RTL Design, DFT and Physical design.

- Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure.

Necessary Qualifications :

- Bachelor's or Master's degree in Electronics, Computer Science Engineering, or a related field

- Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA.

- Experience with Cadence, Synopsys and Mentor tools

- Experience with Verilog and VHDL.

- Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/CPF/CLP)

- Formal verification for RTL 2 gates and gates2gates

- Conformal ECO for doing complex functional ECOs.

- Low power synthesis on smaller blocks and subsystems using DC/Genus

- Physical Aware synthesis

- Writing Timing Constraints sub-blocks and Top level.

- Flow Automation and Scripting using TCL and Python or Perl.