Job Summary :

We are looking for an STA & Synthesis Engineer responsible for timing analysis and logic synthesis of digital designs. The role focuses on achieving timing closure and optimizing design performance, power, and area.

Key Responsibilities :

- Perform RTL synthesis using industry-standard tools

- Should be capable to analyze and run LEC to ensure gate level netlist matches the original RTL

- Run Static Timing Analysis (STA) and identify timing violations

- Fix setup and hold violations across different corners/modes

- Work on constraints development (SDC creation and validation)

- Analyze timing reports and improve design quality

- Collaborate with RTL, DFT, and Physical Design teams

- Support timing closure during implementation and signoff

Required Skills :

- Strong understanding of digital design fundamentals

- Knowledge of synthesis and STA flow

- Familiarity with timing concepts (setup, hold, skew, latency)

- Experience with EDA tools (Experience with EDA tools - (Genus, Tempus)