Spigot Software - Physical Design Engineer

Description :

- Synthesis, DFT, Floorplan, Place and Route, CTS and Optimization of CPU cores, system interconnect and other Arm Designs.

- RTL-GDS closure for Hard Macro.

- Analyse design timing, area and power to help improve the quality of Arm Design.

- Analyse DRC/LVS/PERC/ERC using Calibre and perform Layout edit for Physical Verification closure.

- Analyse timing using primetime and perform Timing ECO for design closure.

- Work with implementation and physical IP RTL design teams to drive analysis and optimisation of our IP.

- Converting R& D concepts into real implementation solutions.

- Enable our partners to achieve the best possible quality of results.

Requirements :

- Mandate skill set : Innovus, Place and Route with 4+ years relevant exp.

- Bachelor's or master's degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.

- 3+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification.

- Strong Communication and Problem-Solving Skills.

- Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams.

- Experience working closely at top and block level Synthesis, DFT, Floor planning, Place and Route, CTS, logical and physical optimisation, timing closure and power analysis flows.

- Proven programming and scripting skills, eg, Tcl, Perl, Python, Make.

- Knowledge around Arm-based SoCs!

- Experience with a wide range of programming, scripting and data presentation languages, Eg, Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, Ruby.

- Experience with low power design techniques (power gating, voltage/frequency scaling).

- Experience with Verilog RTL design.

- Experience with ATPG tools/and or production testing.