Spigot Software - DFT Engineer - RTL/SoC

Description :

Role Overview :

We are looking for an experienced DFT Engineer with strong hands-on expertise in RTL and gate-level DFT implementation across SoC and block-level designs.

The role involves working on complete DFT flows using Mentor Tessent and ARM DFT methodologies, from insertion to verification and coverage closure.

Key Responsibilities :

- Execute DFT tool flows using Mentor Tessent.

- Perform RTL-level DFT implementation, including pre-DFT and post-DFT activities.

- Run Logic Equivalence Checks (LEC) at :

a. RTL level (pre-DFT vs post-DFT)

b. Gate level

- Handle DFT activities at SoC, subsystem, block, and partition levels.

- Perform DFT insertion including :

a. Scan

b. MBIST

c. OCC

d. EDT using ARM DFT flows.

- Generate, retarget, and simulate DFT patterns at both block and SoC levels.

- Perform zero-delay and timing simulations using SDF back-annotation.

- Drive coverage analysis and coverage closure.

- Perform scan synthesis and create timing constraints for DFT.

- Support debug and sign-off activities for DFT readiness.

Required Skills & Experience :

- Strong hands-on experience with Mentor Tessent DFT tools.

- Expertise in RTL and gate-level DFT implementation.

- Experience working on SoC and block-level designs.

- Solid understanding of LEC flows at RTL and gate levels.

- Experience with scan, MBIST, OCC, and EDT insertion.

- Knowledge of pattern generation, retargeting, and simulation.

- Hands-on experience with SDF-based timing simulations.

- Strong understanding of coverage metrics and closure.

- Experience in scan synthesis and timing constraint creation.

Good to Have :

- SSN experience (mandatory / highly preferred)

- Exposure to advanced SoC test methodologies.

- Experience working in multi-foundry or large-scale SoC environments.

Why Join :

- Opportunity to work on complex SoC designs

- End-to-end ownership of DFT implementation and sign-off

- Exposure to industry-standard tools and flows