Softpath Technologies - DFT Lead Engineer - VHDL/Verilog

Position : DFT Lead Engineer

Experience : 8- 10+yrs

Location : Noida -2 months then they can relocate to their location and can work remotely (out of blr candidates)

Job Mode : Work From Office

NOTE : Initial two months they can get paid accommodation along with flight to and fro

Key skills :

- DFT engineer preferably with 8- 10 yrs of experience in SoC DFT implementation and verification of scan architectures, JTAG, boundary scan, memory BIST, ATPG and LBIST. BE/ME/B.Tech/M.Tech from reputed institutes with relevant industry experience

- The engineer should be well versed in Verilog/VHDL RTL coding, automation, experienced in using Mentor DFT tool sets and reasonable acquaintance with Synopsyss scan insertion and timing analysis tools along with standard linting tools.

- The engineer needs to have hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF and post silicon debug.

- Must have worked on more than one SoC , from start to end.

- Must be proactive, collaborative, self-driven and detail-oriented capable of exercising independent judgment

- The engineer with experience on debug and root cause the problem in simulation failures and silicon

- Self-motivation, flexibility, with strong interpersonal skills.

- Effective communication skills, oral and written skills

- Show an engaged curiosity, a will to understand the mechanisms behind the effects, an eagerness to constantly learn and improve

Key Responsibilities :

- Lead and execute DFT architecture definition, implementation, and verification for complex SoCs

- Implement and verify Scan architectures, JTAG, Boundary Scan, Memory BIST, ATPG, and LBIST

- Perform scan insertion, ATPG DRC, fault coverage analysis, and pattern generation

- Debug simulation failures, timing issues (SDF), and post-silicon failures

- Work closely with design, verification, physical design, and silicon teams to resolve DFT-related issues

- Drive post-silicon debug, root cause analysis, and corrective actions

- Ensure DFT sign-off quality and adherence to project timelines

- Automate repetitive flows and improve DFT efficiency through scripting

- Mentor junior engineers and contribute to best practices and process improvements