Softpath Technologies - Design Verification Engineer

Job Title : DV Engineer

Location : Bangalore (Work From Office)

Experience : 5- 10 years

Notice Period : Immediate to 30 Days

Job Description :

We are looking for a highly skilled Design Verification (DV) Engineer with strong expertise in SystemVerilog (SV) and UVM to join our team at ACL Digital. The ideal candidate will have proven hands-on experience in verification methodologies, along with a strong understanding of protocols and functional safety standards.

Key Responsibilities :

- Develop and implement testbenches using SystemVerilog and UVM methodology.

- Perform block-level and subsystem-level verification for complex SoCs/IPs.

- Create, execute, and debug test cases to ensure design quality and coverage closure.

- Collaborate with design, architecture, and validation teams for seamless integration and issue resolution.

- Ensure compliance with functional safety (FuSa/ISO26262) requirements where applicable.

- Work on verification for high-speed protocols such as USB4.0 / USB 3.x / USB 2.x.

- Contribute expertise in one or more MAC Layer protocols (PCIe / USB / WiFi / Bluetooth).

Key Skills (Mandatory) :

- Strong hands-on experience in SystemVerilog (SV) and UVM.

- Solid debugging and problem-solving skills.

Preferred Skills :

- Functional Safety (FuSa) / ISO26262 compliance knowledge.

- Expertise in USB4.0 / USB 3.x / USB 2.x.

- MAC Layer expertise in any one of the following protocols : PCIe / USB / WiFi / Bluetooth.