Softpath Technologies - AMS Verification Engineer - System Verilog

AMS Verification Engineer SerDes / Mixed-Signal | 5+ Years Experience | Bangalore / Pune

Key Responsibilities :

Verification Development :

- Develop comprehensive verification environments using SystemVerilog and UVM from the ground up.

- Build self-checking testbenches for verifying mixed-signal IPs and subsystems.

- Drive testbench architecture, stimulus generation, scoreboarding, and coverage closure.

AMS Co-Simulation :

- Integrate and run AMS co-simulations using tools such as Synopsys VCS AMS, Primesim AMS, and XA.

- Collaborate closely with design and modeling teams to bring up analog and digital blocks in a unified simulation environment.

- Debug AMS simulations and root-cause analog-digital interaction issues.

Modeling and Abstraction :

- Use and develop analog behavioral models using Verilog-A, wreal, and Real Number Modeling (RNM) techniques.

- Implement efficient analog abstraction models for faster regression simulations.

Test Planning & Execution :

- Define and document verification plans (testplans) based on design specifications and functional requirements.

- Track test progress, update verification status, and drive test coverage and signoff.

- Participate in code reviews, testplan reviews, and contribute to overall verification methodology.

Protocol & IP Verification :

- Perform IP-level and sub-system-level verification for high-speed protocols such as PCIe, USB 3.0, MIPI, or other SerDes standards.

- Validate timing, control, calibration sequences, power states, and compliance requirements.

Cross-Team Collaboration :

- Work with digital design, analog design, modeling, and validation teams across different geographies.

- Help in the integration of IP into SoC-level verification environments when needed.

Skills & Tools :

Required Skills :

- Strong experience in SystemVerilog and UVM-based verification.

- Hands-on expertise with VCS AMS, Primesim AMS, or XA.

- Deep understanding of wreal, RNM, and Verilog-A modeling.

- Experience with analog and digital co-simulation flows.

Protocol Knowledge :

- Good understanding and working knowledge of one or more high-speed protocols : PCIe, USB 3.0, MIPI, etc.

- Familiarity with SerDes architecture, clocking schemes, and calibration mechanisms.

Preferred (Good to Have) :

- Experience in low power verification, DFT, or formal verification.

- Exposure to mixed-signal behavioral modeling techniques or MATLAB/Simulink modeling.

Location :

Primary : Bangalore or Pune

Hybrid / Remote : Optional based on candidate experience and team needs

Experience :

5+ years of industry experience in AMS or Mixed-Signal Verification