We are seeking an experienced SoC RTL Design Engineer with strong expertise in IP and subsystem design, RTL development, and SoC-level integration. The ideal candidate will have deep knowledge of RTL quality methodologies, AMBA protocols, timing concepts, and industry-standard design tools. The role requires collaboration across design, verification, physical design, DFT, and firmware teams to deliver high-quality, production-ready SoC designs.

Key Responsibilities :

IP / Subsystem / SoC Architecture & Design :

- Lead and contribute to IP, subsystem/cluster, and SoC-level RTL design using Verilog/SystemVerilog.

- Analyze architectural requirements and translate them into efficient, synthesizable RTL.

- Drive subsystem integration, ensuring compatibility across interfaces and seamless connectivity within the SoC.

RTL Quality & Methodology :

- Perform and ensure compliance with RTL quality checks including Lint, CDC, and reset-domain validation.

- Use tools such as SpyGlass Lint/CDC or equivalent to enforce quality metrics and design robustness.

- Support synthesis teams by ensuring RTL meets structural, timing, and coding standards.

Synthesis, Low Power & Timing :

- (Preferred) Support synthesis flows using Synopsys Design Compiler (DC) and understand timing constraints, multi-clock designs, and timing closure techniques.

- Assist in applying or reviewing low-power architecture, UPF flows, or clock gating strategies.

- Collaborate with physical design teams to resolve timing, congestion, and structural issues.

Interface Protocols & Bus Architecture :

- Demonstrate strong understanding of AMBA protocols including AXI, AHB, ATB, and APB.

- Design and integrate one or more high-speed or peripheral interfaces, such as :

PCIe
DDR
Ethernet
I2C, UART, SPI

- Support end-to-end subsystem functionality, protocol compliance, and performance optimization.

- Debugging & Cross-Functional Support

- Debug complex RTL and integration issues across multiple subsystems using tools like Verdi, Xcelium, or equivalent simulators.

- Provide design support to verification, physical design, DFT, and software teams throughout development.

- Participate in design reviews, identify potential issues early, and ensure best practices across teams.

- Documentation & Technical Leadership

- Create, review, and maintain design specification documents, architecture descriptions, and integration guides.

- Help guide junior engineers, review their work, and ensure quality across multiple subsystems.

- Provide technical leadership in design, integration, and debugging activities.

Automation & Scripting :

- Develop scripts using Make, Perl, Shell, or Python to automate workflows, improve productivity, and streamline design processes.

Required Skills & Qualifications :

- Strong expertise in SoC IP and subsystem design using Verilog/SystemVerilog.

- Proven experience in SoC or subsystem-level RTL integration.

- In-depth knowledge of RTL quality checks (Lint, CDC) and relevant tools like SpyGlass.

- Solid understanding of AMBA bus protocols (AXI, AHB, ATB, APB).

- Good grasp of timing concepts, multi-clock domain design, and synchronizers.

- Hands-on experience with tools like:

- SpyGlass Lint/CDC

- Synopsys Design Compiler (DC)

- Verdi / Xcelium

- Proficiency in scripting using Make, Perl, Shell, Python, etc.

Preferred Qualifications:
- Understanding of processor architecture and/or ARM debug architecture.

- Exposure to low-power design methodologies, UPF, or clock/power gating.

- Experience supporting physical design, verification, DFT, or software teams.

- Prior experience handling multiple subsystems in complex SoC programs.