SoC Design Verification Engineer

Description :

Role : SOC DV

Experience : 5+Years

Location : Bangalore

Employee Type : Full Time

Notice Period : 15 Days

Key Responsibilities :

- Develop and execute SystemVerilog-based testbenches for SoC and subsystem verification.

- Verify SoC interconnects and IP integration using AMBA protocols (AXI, AHB, APB).

- Create and maintain directed and constrained-random tests.

- Debug simulation failures, analyze waveforms, and work with designers to resolve issues.

- Apply UVM methodology for environment development and test automation.

- Participate in verification planning, coverage analysis, and regression execution.

Required Skills :

- Strong understanding of AMBA bus protocols AXI, AHB, and APB.

- Good knowledge of SystemVerilog for design verification.

- Basic programming skills in C language (for firmware or test stimulus).

- Strong debugging skills and experience with simulation tools (e.g., VCS, Questa, Incisive).

- Basic understanding of UVM (Universal Verification Methodology).