- As the Hardware Design Verification Engineer, you will develop the verification methodology for SiMa.ais MLSoC. You will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams.

- Areas of focus : Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team.

Minimum Qualifications :

- BS in Computer Science/EE with 4+ years of experience or MS in Computer Science/EE with 2+ years of experience in HW Design Verification.

- Experience with block level, cluster level or chip/SoC level verification.

- Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog.

- Expertise in scripting languages, python or perl.

- Strong experience in helping emulation and validation.

- Experience with modeling various HW blocks, IPs for verification, emulation.

- Ability to analyze systems-level performance, profiling, and analysis.

Preferred Qualifications :

- ML experience

- C/C++

Personal attributes :

- Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.