Role Overview :

The RTL Design Engineer for Mixed-Signal IPs is responsible for developing, integrating, and verifying digital RTL blocks within mixed-signal subsystems that combine analog and digital functionalities.

This role requires a deep understanding of digital design principles, interface with analog/mixed-signal teams, and strong verification and integration skills to ensure high-quality, low-power, and functionally robust IP delivery.

The engineer will work closely with system architects, analog designers, and SoC teams to enable seamless integration of mixed-signal IPs into complex SoCs.

Key Responsibilities :

- Develop synthesizable, high-quality RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends.

- Collaborate with analog design engineers to define digital-analog interface specifications, control logic, and communication protocols.

- Ensure correct functionality and performance of mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components.

- Participate in design reviews, micro-architecture definition, and documentation of IP functionality and timing interfaces.

- Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.

- Collaborate with verification engineers to define test plans, drive coverage closure, and debug issues across digital and analog boundaries.

- Integrate mixed-signal IPs into SoC top-level RTL and resolve functional or timing issues during full-chip validation.

- Contribute to continuous improvement of design methodologies, automation scripts, and reuse strategies for mixed-signal IP development.

Qualifications :

- 5-10 years of experience in digital RTL design with strong exposure to mixed-signal IP or subsystem development.

- Proficiency in Verilog/SystemVerilog and experience with synthesis and static verification flows (lint, CDC).

- Familiarity with analog/mixed-signal concepts such as signal sampling, clocking, calibration, and power management.

- Hands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS, etc.) is a plus.

- Good understanding of digital communication protocols (SPI, I2C, APB, AXI).

- Exposure to scripting (Python, Perl, TCL) for automation and design flow enhancements.

- Experience working in cross-functional environments involving analog, verification, and SoC integration teams.

Education : B.E/B.Tech or M.E/M.Tech in Electrical Engineering, Electronics, or Computer Engineering.

Key Competencies :

- Strong understanding of digital design and verification fundamentals.

- Ability to work effectively across analog and digital domains in a collaborative environment.

- Excellent debugging, problem-solving, and analytical skills.

- Good communication and documentation abilities.

- Passion for quality, efficiency, and innovation in mixed-signal IP design.

Success Metrics :

- Timely delivery of functionally correct and synthesis-ready RTL for mixed-signal IPs.

- High quality and robustness verified through simulation, lint, and CDC sign-off.

- Effective collaboration with analog and SoC teams ensuring smooth IP integration.

- Contributions to methodology and flow improvements enhancing team efficiency.

Benefits & Perks :

- Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

- Equity Rewards (RSUs)

- Employee Stock Purchase Plan (ESPP)

- Insurance plans with Outpatient cover

- National Pension Scheme (NPS)

- Flexible work policy

- Childcare support