- Lead SoC and subsystem-level functional verification activities from planning to closure.

- Define verification strategies, methodologies, and environments using SystemVerilog and UVM.

- Develop and maintain scalable, reusable UVM-based testbenches for complex IPs and SoCs.

- Drive verification plans for high-speed interfaces like PCIe, CXL, AMBA (AXI, AHB, APB), and CPU subsystems.

- Define and implement coverage-driven and assertion-based verification methodologies (CDV/ABV).

- Own coverage closure, regression analysis, and final sign-off metrics for quality and completeness.

- Debug complex functional, performance, and timing issues in collaboration with design and validation teams.

- Execute and oversee Gate-Level Simulations (GLS), waveform analysis, and issue triaging.

- Evaluate and adopt emerging verification methodologies and tools to improve efficiency and scalability.

- Contribute to verification automation frameworks, flow enhancements, and continuous improvement initiatives.

- Act as a technical mentor and reviewer for mid-level and junior DV engineers.

- Collaborate with program managers and cross-functional stakeholders to ensure timely project delivery.

Technical Skills & Expertise :

- 15+ years of experience in Design Verification for ASICs / SoCs.

- Expert-level proficiency in SystemVerilog, UVM, and functional verification flows.

- In-depth understanding of SoC architectures, CPU subsystems, and interconnect protocols.

- Strong exposure to AMBA (AXI, AHB, APB) and high-speed interfaces like PCIe or CXL.

- Proven experience with Gate-Level Simulations (GLS) and low-power verification methodologies.

- Solid debugging skills using waveform viewers, simulators (VCS, Questa, Xcelium), and regression tools.

- Hands-on experience with coverage closure, constrained-random verification, and automation scripting (Python, Perl, TCL).

- Familiarity with formal verification, emulation, or FPGA prototyping environments is a plus.

- Strong analytical, documentation, and communication skills.

Leadership & Soft Skills :

- Proven experience in leading verification teams or mentoring engineers.

- Ability to own end-to-end verification sign-off for complex SoCs.

- Strong collaboration skills able to work effectively with design, architecture, and validation groups.

- Strategic thinker with the ability to balance hands-on technical execution and leadership.

- Excellent communication and presentation abilities