As a Senior RTL Design Engineer, you will be responsible for developing, implementing, and validating FPGA designs on Xilinx Zynq UltraScale+ platforms. You will collaborate closely with cross-functional teams to deliver optimized and reliable digital design solutions.

Key Responsibilities :

- Design, develop, and verify FPGA modules using Verilog.

- Perform synthesis, simulation, and implementation using Xilinx Vivado.

- Develop and optimize solutions on Xilinx Zynq UltraScale+ FPGA platforms.

- Integrate and interface peripherals such as I2C, SPI, DDR, EMMC, AMBA, PL, PS, etc.

- Work closely with hardware, software, and system teams for end-to-end design execution.

Required Skills & Qualifications :

- 5+ years of strong RTL design experience using Verilog.

- Bachelors or Masters degree in Electronics / Computer Engineering or related field.

- Hands-on expertise with Xilinx Vivado design suite.

- Strong understanding of FPGA architecture, synthesis flow, and timing closure.

- Experience with Xilinx Zynq UltraScale+ FPGA family.

- Proficiency in interfacing protocols : I2C, SPI, DDR, EMMC, AMBA, etc.

Nice to Have :

- Experience in high-speed signal design.