Job Overview:

We are a leading Optical Wireless Communication (OWC) company developing next-generation LiFi and Free-Space Optical (FSO) technologies. This is an R&D position where you will own the design, development, and experimental validation of physical layer algorithms from theoretical formulation and simulation through to FPGA prototyping. Both publishing and hardware prototyping are highly encouraged and expected in this role.

Key Responsibilities:

- Algorithm Design: Create PHY algorithms for LiFi and FSO systems, focusing on modulation (OOK, PPM, DCO-OFDM, ACO-OFDM), channel coding (LDPC, Polar, RS), and synchronization.

- Channel Modelling: Model and simulate optical wireless channels, accounting for atmospheric turbulence, pointing errors, receiver noise, ambient light interference, and LED/laser non-linearities.

- Link-Level Simulation: Build end-to-end simulation chains from scratch using MATLAB or Python to evaluate BER, throughput, and spectral efficiency.

- FPGA Implementation: Translate fixed-point models into RTL or HLS, and handle hardware validation on FPGA targets.

- Reference Models: Write bit-exact C/C++ reference models to directly support hardware verification workflows.

- Standards Engagement: Track and implement specifications from relevant standards, including IEEE 802.11bb (LiFi) and ITU-T FSO.

Required Skills & Qualifications:

- Education: M.Tech, M.S., or Ph.D. in ECE, Electrical Engineering, Signal Processing, or a related field.

- Digital Communications: Deep understanding of modulation, channel coding, detection, estimation, and synchronization.

- Simulation Mastery: Hands-on experience building custom PHY simulations from scratch in MATLAB or Python.

- OFDM Systems: Solid grasp of multipath channels, cyclic prefix, pilot design, and channel estimation.

- Hardware Awareness: Ability to implement fixed-point architectures while managing quantization effects and hardware cost constraints.

- RTL & Tooling: Proficiency in VHDL or Verilog to review/write RTL for PHY blocks, alongside hands-on exposure to AMD/Xilinx Vivado for synthesis and timing closure.