Senior DFT Engineer - EDA Tools

We are hiring for Senior DFT Engineer with 2-3 Years of Experience for Hyderabad location

Notice Period : Immediate / 2 weeks preferred.

Below the jd. :

- DFT pattern generation, verification and delivery to ATE team.

- Gate Level simulation with and without timing. Post silicon experience and support on failing patterns.

- Good experience on EDA tools of reputed vendor like Mentor, Synopsis.

Job Description :

- Candidate to generate ATPG patterns for different fault models SAF/TDF/IDDQ etc. Simulate them in Notiming & Timing.

- Release them for ATE validation & support any post silicon debug, if required.

Key Skills & Technical Expertise :

- DFT pattern generation, verification, and delivery to the ATE team

- ATPG pattern generation for various fault models : SAF, TDF, IDDQ, etc.

- Gate-level simulation with and without timing

- Post-silicon debug and support for failing patterns

- Strong hands-on experience with EDA tools from reputed vendors such as Mentor Graphics and Synopsys

- Understanding of scan architecture, fault coverage, and test methodologies

- Good knowledge of digital design fundamentals

Roles & Responsibilities :

- Generate ATPG patterns for different fault models including SAF, TDF, and IDDQ

- Perform no-timing and timing gate-level simulations to validate test patterns

- Analyze coverage results and optimize patterns for improved fault coverage

- Release validated patterns to the ATE team and support ATE correlation activities

- Provide post-silicon debug support and assist in resolving failing patterns

- Collaborate with design, verification, and silicon validation teams

- Document test methodologies, pattern results, and debug findings

- BE / BTech in Electronics, Electrical, or related discipline

- Strong analytical and debugging skills

- Ability to work closely with cross-functional teams

- Good communication and documentation skills.