Senior Design Verification Engineer - Embedded System

Open Positions :

- Senior PCIe Verification Engineer (8+ yrs) : Expertise in Gen3 - Gen6, UVM, protocol compliance, Root Complex & Endpoint.

- SoC NoC Verification Lead (10+ yrs) : Leadership role with SystemVerilog/UVM, AXI/CHI/CXL/PCIe/UCIe, debug & coverage optimization.

- NoC SoC Verification Engineer (7+ yrs) : Functional/performance/power verification, testbench development, protocol-level validation.

- Wireless Protocol DV Engineer : Experience with eCPRI, Ethernet, JESD, PTP, FEC, and O-RAN IPs.

- Complex Testbench & Low-Power Verification Expert : Verilog/SV/SystemC, coverage-driven verification, UPF/NLP, random test gen, scripting (C/C++, Perl, Shell).

Key Skills We Value :

- System Verilog/UVM, Verilog, SystemC.

- AXI, CHI, PCIe, Ethernet, CXL, UCIe, eCPRI, JESD.

- Power-aware verification (UPF/NLP).

- Debug skills, random test gen, coverage closure.

- Strong scripting and automation mindset.

- Leadership & collaboration.