Senior AMS Verification Engineer

AMS Verification Senior Engineer (4 - 7 yrs)

- Perform mixed-signal simulations and analyze results to ensure compliance with design specifications.

- Define and track functional and coverage metrics; write coverage models and monitor progress.

- Identify, debug, and resolve mismatches between expected and actual simulation results.

- Collaborate with analog, digital, and modeling teams to resolve verification issues and improve test coverage.

Requirements :

- Strong understanding of analog/mixed-signal modeling and verification flows.

- Experience in using tools such as Cadence AMS Designer, Synopsys VCS AMS, or similar.

- Proficiency in scripting languages (e.g., Python, Perl, Shell) for automation and debugging.

- Solid knowledge of mixed-signal debug methodologies and waveform analysis.

- Familiarity with Verilog-AMS, SystemVerilog, SPICE, and behavioral modeling.

- Excellent problem-solving skills and ability to work in a cross-functional team environment